How to use _write_body method in Slash

Best Python code snippet using slash

file_writer.py

Source:file_writer.py

...114        contents = output.getvalue()115        output.close()116        return contents117    118    def _write_body(self, *args, **kwargs):119        self._body.append(self._print_to_string(*args, **kwargs))120    def _write_header(self, *args, **kwargs):121        self._header.append(self._print_to_string(*args, **kwargs))122    def _write_trailer(self, *args, **kwargs):123        self._trailer.append(self._print_to_string(*args, **kwargs))124    def _write_signal(self, declaration: DeclarationData):125        self._signals.append(VhdlSignal(instance=declaration.instance_name, 126        name=declaration.entity_name, type=declaration.type))127    def _flatten(self, xss: List[List[str]]) -> List[str]:128        return [x for xs in xss for x in xs]129    def _write_component_instantiation_generic_map(self, instance: InstanceData) -> None:130        if instance.generic_map is not None:131            self._write_body("generic map (")132            self._write_body("; ".join(instance.generic_map))133            self._write_body(")")134    def _get_component_instantiation_memory_port_map(self, instance: InstanceData) -> List[str]:135        self._msg.function_start(f"instance={instance}")136        vhdl_memory_port = VhdlMemoryPort()137        memory_port_map = []138        if instance.memory_interface is not None:139            master = instance.memory_interface.is_master()140            memory_port_map = vhdl_memory_port.get_port_map(name=instance.instance_name, master=master)141            self._instance_signals.extend(vhdl_memory_port.get_port_signals(name=instance.instance_name))142        self._msg.function_end(memory_port_map)143        return memory_port_map144 145    def _get_input_port_map(self, input_port: InstructionArgument, instance: InstanceData) -> List[str]:146        vhdl_port = VhdlPortGenerator()147        memory_interface_name = instance.get_memory_port_name(port=input_port)148        if memory_interface_name is not None:149            vhdl_memory_port = VhdlMemoryPort()150            self._instance_signals.extend(vhdl_memory_port.get_port_signals(name=memory_interface_name))151        return vhdl_port.get_port_map(input_port=input_port, memory_interface_name=memory_interface_name)152    def _get_input_port_maps(self, instance: InstanceData) -> List[str]:153        self._msg.function_start(f"instance={instance}")154        input_ports_map = [self._get_input_port_map(input_port=i, instance=instance) for i in instance.input_ports]155        result = self._flatten(input_ports_map)156        self._msg.function_end(result)157        return result158    def _write_component_instantiation_port_map(self, instance: InstanceData) -> None:159        self._msg.function_start(f"instance={instance}")160        vhdl_port = VhdlPortGenerator()161        memory_port_map = self._get_component_instantiation_memory_port_map(instance=instance)162        input_ports_map = self._get_input_port_maps(instance=instance)163        tag_port_map = [f"s_tag => {self._local_tag_in}", f"m_tag => {self._local_tag_out}"]164        standard_port_map =  vhdl_port.get_standard_ports_map(instance=instance)165        output_port_map = [] if instance.output_port.is_void() else vhdl_port.get_output_port_map(output_port=instance.output_port)166        ports = input_ports_map + output_port_map + memory_port_map + standard_port_map + tag_port_map167        self._write_body(", ".join(ports), end="")168        self._msg.function_end(None)169    def _write_component_instantiation(self, instance: InstanceData) -> None:170        self._msg.function_start(f"instance={instance}")171        self._write_body(f"{instance.instance_name} : entity {instance.library}.{instance.entity_name}")172        self._write_component_instantiation_generic_map(instance=instance)173        self._write_body("port map (", end="")174        self._write_component_instantiation_port_map(instance=instance)175        self._write_body(");")176        self._msg.function_end(None)177    def _write_component_output_signal_assignment(self, instance: InstanceData) -> None:178        self._msg.function_start(f"instance={instance}")179        self._write_body("process (all)")180        self._write_body("begin")181        self._write_body(f"{instance.tag_name} <= conv_tag({self._local_tag_out});")182        if not instance.output_port.is_void():183            self._write_body(f"{instance.tag_name}.{instance.instance_name} <= m_tdata_i;")184        self._write_body("end process;")185        self._msg.function_end(None)186        187    def _write_instance_signals(self, instance: InstanceData) -> None:188        vhdl_port = VhdlPortGenerator()189        input_ports_signals = [vhdl_port.get_port_signal(input_port=i) for i in instance.input_ports]190        self._write_body("signal tag_i : tag_t;")191        self._write_body(f"signal {self._local_tag_in}, {self._local_tag_out} : std_ulogic_vector(0 to c_tag_width - 1);")192        for i in input_ports_signals:193            self._write_body(i)194        self._write_body(f"signal m_tdata_i : {instance.output_port.get_type_declarations()};")195    def _write_instance_signal_assignments(self, instance: InstanceData) -> None:196        vhdl_port = VhdlPortGenerator()197        input_ports_signal_assignment = [vhdl_port.get_port_signal_assignment(input_port=i, ports=self._ports, signals=self._signals) for i in instance.input_ports]198        tag_name = instance.get_previous_instance_signal_name("tag_out")199        self._write_body("tag_i <= " + ("tag_in_i" if tag_name is None else tag_name) + ";")200        self._write_body(f"{self._local_tag_in} <= tag_to_std_ulogic_vector(tag_i);")201        for i in input_ports_signal_assignment:202            self._write_body(i)203    204    def _write_instance(self, instance: InstanceData) -> None:205        self._msg.function_start(f"instance={instance}")206        if instance.library != "work":207            self._instances.append(instance.entity_name)208        vhdl_port = VhdlPortGenerator()209        self._instance_signals.extend(vhdl_port.get_standard_ports_signals(instance=instance))210        block_name = f"{instance.instance_name}_b"211        self._write_body(f"{block_name} : block")212        self._write_instance_signals(instance=instance)213        self._write_body("begin")214        self._write_instance_signal_assignments(instance=instance)215        self._write_component_instantiation(instance=instance)216        self._write_component_output_signal_assignment(instance=instance)217        self._write_body(f"end block {block_name};")218        self._msg.function_end(None)219    def _get_ports(self, port: Port) -> List[str]:220        return VhdlPortGenerator().get_ports(port)221    def _write_ports(self, ports: List[Port]) -> None:222        self._write_header("port (")223        xss = [self._get_ports(i) for i in ports if not i.is_void()]224        x = self._flatten(xss) 225        standard_ports = VhdlPortGenerator().get_standard_ports_definition()226        tag_ports = ["s_tag : IN std_ulogic_vector", "m_tag : out std_ulogic_vector"] 227        self._write_header(";\n".join(x + standard_ports + tag_ports))228        self._write_header(");")229    def _write_instances(self, instances: InstanceContainerData, ports: List[Port]) -> None:230        self._msg.function_start(f"instances={instances}, ports={ports}")231        self._write_body("tag_in_i.tag <= s_tag;")232        for i in ports:233            if i.is_input():234                self._write_body(f"tag_in_i.{i.get_name()} <= {i.get_name()};")235        for j in instances.instances:236            self._write_instance(instance=j)237        return_driver = instances.get_return_instruction_driver()238        self._write_body(f"m_tvalid <= {return_driver}_m_tvalid_i;")239        self._write_body(f"{return_driver}_m_tready_i <= m_tready;")240        output_port_is_void = any((not i.is_input()) and i.is_void() for i in ports)241        if not output_port_is_void:242            self._write_body(f"m_tdata <= conv_std_ulogic_vector(tag_out_i.{return_driver}, m_tdata'length);")243        self._write_body("m_tag <= tag_out_i.tag;")244        self._msg.function_end(None)245    def _write_memory_arbiter_port_map(self, memory_master_name: str, memory_slave_name: str) -> None:246        vhdl_memory_port = VhdlMemoryPort()247        slave_memory_port_map = vhdl_memory_port.get_port_map(name=memory_slave_name, master=False)248        master_memory_port_map = vhdl_memory_port.get_port_map(name=memory_master_name, master=True)249        memory_port_map = slave_memory_port_map + master_memory_port_map250        self._write_body(", ".join(memory_port_map))251    def _write_memory_arbiter(self, instances: InstanceContainerData, memory_name: str) -> None:252        self._msg.function_start(f"instances={instances}, memory_name={memory_name}")253        vhdl_memory_port = VhdlMemoryPort()254        block_name = f"arbiter_{memory_name}_b"255        self._write_body(f"{block_name}: block")256        memory_instance_names = instances.get_memory_instance_names()257        number_of_memory_instances = len(memory_instance_names)258        self._write_body(f"constant c_size : positive := {number_of_memory_instances};")259        memory_signal_name = "s"260        signals = "\n".join([f"signal {i}; " for i in vhdl_memory_port.get_port_signals(name=memory_signal_name, scale_range="c_size")])261        self._write_body(signals)262        self._write_body("begin")263        signal_assigments = "\n".join([f"{i};" for i in vhdl_memory_port.get_signal_assignments(signal_name=memory_signal_name, assignment_names=memory_instance_names)])264        self._write_body(signal_assigments)265        memory_interface_name = f"memory_arbiter_{memory_name}"266        self._write_body(f"{memory_interface_name}: entity memory.arbiter(rtl)")267        self._write_body("port map(clk => clk, sreset => sreset,")268        self._write_memory_arbiter_port_map(memory_master_name=memory_name, memory_slave_name=memory_signal_name)269        self._write_body(");")270        self._write_body(f"end block {block_name};")271        self._msg.function_end(None)272    def _write_all_memory_arbiters(self, instances: InstanceContainerData, memory_port_names: List[str]) -> None:273        self._msg.function_start(f"instances={instances}, memory_port_names={memory_port_names}")274        for memory_name in instances.get_memory_names() + memory_port_names:275            self._write_memory_arbiter(instances=instances, memory_name=memory_name)276        self._msg.function_end(None)277    def _write_declarations(self, declarations: List[DeclarationData]):278        for i in declarations:279            self._write_signal(declaration=i)280    def write_constant(self, constant: ConstantDeclaration):281        self._constants.append(Constant(constant))282    def _write_include_libraries(self) -> None:283        self._write_header("library ieee;")284        self._write_header("use ieee.std_logic_1164.all;")...

event.py

Source:event.py

...163        self.tz = self.context.start().timezone()164        self.start = self.mk_iCal(self.context.start())165        self.end = self.mk_iCal(self.context.end())166        self.UID = "%s-%s" %(self.context.Title(), self.creation_date)167        return self._write_body()168    def _write_body(self):169        response = self.request.response170        body = ViewPageTemplateFile('templates/event_ical.pt')(self)171        response.setHeader('Content-Type', 'text/iCal')172        response.setHeader('Content-Disposition', 'filename=cmf.ics')173        response.write(body.encode("UTF-8"))174class EventvCalView(EventiCalView):175    """vCal view"""176    def _write_body(self):177        response = self.request.response178        body = ViewPageTemplateFile('templates/event_vcal.pt')(self)179        response.setHeader('Content-Type', 'text/vCal')180        response.setHeader('Content-Disposition', 'filename=cmf.vcs')...

fusioncgi.py

Source:fusioncgi.py

...50        for k, v in self._header.items():51            self._write(k + ": " + v + "\n")52        self._write_cookie()53        self._write("\n\n")54    def _write_body(self, data):55        self._write(data)56        self._flush()57    def _write_done(self, data):58        self._write_head()59        self._write_body(data)60        exit(0)61    def set_header(self, header):62        self._header.update(header)63    def set_cookie(self, cookie):64        if isinstance(cookie, BaseCookie):65            self._cookie.update(cookie)66    def json(self, data, cookie=None):67        if "Content-Type" not in Response._header:68            self.set_header({"Content-Type": "application/json"})69        self.set_cookie(cookie)70        self._write_done(json.dumps(data))71    def sse_head(self, cookie=None):72        if "Content-Type" not in Response._header:73            self.set_header({"Content-Type": "text/event-stream"})74        self.set_cookie(cookie)75        self._write_head()76    def sse_body(self, data):77        self._write_body("data: {}\n\n".format(data))78    def sse_json(self, data):79        self.sse_body(json.dumps(data))80Response = _Response()81class DataManage:82    def __init__(self, name):83        self.__filepath = name84        self.__shelve = None85    def __enter__(self):86        self.__shelve = shelve.open(self.__filepath, writeback=True)87        return self.__shelve88    def __exit__(self, exit_type, exit_value, exit_trace):89        self.__shelve.close()90class Session:91    def __init__(self, sid):...

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