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How to use Register method of x86 Package
Best Syzkaller code snippet using x86.Register
arch.go
Source:arch.go 
...28 *obj.LinkArch29 // Map of instruction names to enumeration.30 Instructions map[string]obj.As31 // Map of register names to enumeration.32 Register map[string]int1633 // Table of register prefix names. These are things like R for R(0) and SPR for SPR(268).34 RegisterPrefix map[string]bool35 // RegisterNumber converts R(10) into arm.REG_R10.36 RegisterNumber func(string, int16) (int16, bool)37 // Instruction is a jump.38 IsJump func(word string) bool39}40// nilRegisterNumber is the register number function for architectures41// that do not accept the R(N) notation. It always returns failure.42func nilRegisterNumber(name string, n int16) (int16, bool) {43 return 0, false44}45// Set configures the architecture specified by GOARCH and returns its representation.46// It returns nil if GOARCH is not recognized.47func Set(GOARCH string, shared bool) *Arch {48 switch GOARCH {49 case "386":50 return archX86(&x86.Link386)51 case "amd64":52 return archX86(&x86.Linkamd64)53 case "arm":54 return archArm()55 case "arm64":56 return archArm64()57 case "mips":58 return archMips(&mips.Linkmips)59 case "mipsle":60 return archMips(&mips.Linkmipsle)61 case "mips64":62 return archMips64(&mips.Linkmips64)63 case "mips64le":64 return archMips64(&mips.Linkmips64le)65 case "ppc64":66 return archPPC64(&ppc64.Linkppc64)67 case "ppc64le":68 return archPPC64(&ppc64.Linkppc64le)69 case "riscv64":70 return archRISCV64(shared)71 case "s390x":72 return archS390x()73 case "wasm":74 return archWasm()75 }76 return nil77}78func jumpX86(word string) bool {79 return word[0] == 'J' || word == "CALL" || strings.HasPrefix(word, "LOOP") || word == "XBEGIN"80}81func jumpRISCV(word string) bool {82 switch word {83 case "BEQ", "BEQZ", "BGE", "BGEU", "BGEZ", "BGT", "BGTU", "BGTZ", "BLE", "BLEU", "BLEZ",84 "BLT", "BLTU", "BLTZ", "BNE", "BNEZ", "CALL", "JAL", "JALR", "JMP":85 return true86 }87 return false88}89func jumpWasm(word string) bool {90 return word == "JMP" || word == "CALL" || word == "Call" || word == "Br" || word == "BrIf"91}92func archX86(linkArch *obj.LinkArch) *Arch {93 register := make(map[string]int16)94 // Create maps for easy lookup of instruction names etc.95 for i, s := range x86.Register {96 register[s] = int16(i + x86.REG_AL)97 }98 // Pseudo-registers.99 register["SB"] = RSB100 register["FP"] = RFP101 register["PC"] = RPC102 if linkArch == &x86.Linkamd64 {103 // Alias g to R14104 register["g"] = x86.REGG105 }106 // Register prefix not used on this architecture.107 instructions := make(map[string]obj.As)108 for i, s := range obj.Anames {109 instructions[s] = obj.As(i)110 }111 for i, s := range x86.Anames {112 if obj.As(i) >= obj.A_ARCHSPECIFIC {113 instructions[s] = obj.As(i) + obj.ABaseAMD64114 }115 }116 // Annoying aliases.117 instructions["JA"] = x86.AJHI /* alternate */118 instructions["JAE"] = x86.AJCC /* alternate */119 instructions["JB"] = x86.AJCS /* alternate */120 instructions["JBE"] = x86.AJLS /* alternate */121 instructions["JC"] = x86.AJCS /* alternate */122 instructions["JCC"] = x86.AJCC /* carry clear (CF = 0) */123 instructions["JCS"] = x86.AJCS /* carry set (CF = 1) */124 instructions["JE"] = x86.AJEQ /* alternate */125 instructions["JEQ"] = x86.AJEQ /* equal (ZF = 1) */126 instructions["JG"] = x86.AJGT /* alternate */127 instructions["JGE"] = x86.AJGE /* greater than or equal (signed) (SF = OF) */128 instructions["JGT"] = x86.AJGT /* greater than (signed) (ZF = 0 && SF = OF) */129 instructions["JHI"] = x86.AJHI /* higher (unsigned) (CF = 0 && ZF = 0) */130 instructions["JHS"] = x86.AJCC /* alternate */131 instructions["JL"] = x86.AJLT /* alternate */132 instructions["JLE"] = x86.AJLE /* less than or equal (signed) (ZF = 1 || SF != OF) */133 instructions["JLO"] = x86.AJCS /* alternate */134 instructions["JLS"] = x86.AJLS /* lower or same (unsigned) (CF = 1 || ZF = 1) */135 instructions["JLT"] = x86.AJLT /* less than (signed) (SF != OF) */136 instructions["JMI"] = x86.AJMI /* negative (minus) (SF = 1) */137 instructions["JNA"] = x86.AJLS /* alternate */138 instructions["JNAE"] = x86.AJCS /* alternate */139 instructions["JNB"] = x86.AJCC /* alternate */140 instructions["JNBE"] = x86.AJHI /* alternate */141 instructions["JNC"] = x86.AJCC /* alternate */142 instructions["JNE"] = x86.AJNE /* not equal (ZF = 0) */143 instructions["JNG"] = x86.AJLE /* alternate */144 instructions["JNGE"] = x86.AJLT /* alternate */145 instructions["JNL"] = x86.AJGE /* alternate */146 instructions["JNLE"] = x86.AJGT /* alternate */147 instructions["JNO"] = x86.AJOC /* alternate */148 instructions["JNP"] = x86.AJPC /* alternate */149 instructions["JNS"] = x86.AJPL /* alternate */150 instructions["JNZ"] = x86.AJNE /* alternate */151 instructions["JO"] = x86.AJOS /* alternate */152 instructions["JOC"] = x86.AJOC /* overflow clear (OF = 0) */153 instructions["JOS"] = x86.AJOS /* overflow set (OF = 1) */154 instructions["JP"] = x86.AJPS /* alternate */155 instructions["JPC"] = x86.AJPC /* parity clear (PF = 0) */156 instructions["JPE"] = x86.AJPS /* alternate */157 instructions["JPL"] = x86.AJPL /* non-negative (plus) (SF = 0) */158 instructions["JPO"] = x86.AJPC /* alternate */159 instructions["JPS"] = x86.AJPS /* parity set (PF = 1) */160 instructions["JS"] = x86.AJMI /* alternate */161 instructions["JZ"] = x86.AJEQ /* alternate */162 instructions["MASKMOVDQU"] = x86.AMASKMOVOU163 instructions["MOVD"] = x86.AMOVQ164 instructions["MOVDQ2Q"] = x86.AMOVQ165 instructions["MOVNTDQ"] = x86.AMOVNTO166 instructions["MOVOA"] = x86.AMOVO167 instructions["PSLLDQ"] = x86.APSLLO168 instructions["PSRLDQ"] = x86.APSRLO169 instructions["PADDD"] = x86.APADDL170 // Spellings originally used in CL 97235.171 instructions["MOVBELL"] = x86.AMOVBEL172 instructions["MOVBEQQ"] = x86.AMOVBEQ173 instructions["MOVBEWW"] = x86.AMOVBEW174 return &Arch{175 LinkArch: linkArch,176 Instructions: instructions,177 Register: register,178 RegisterPrefix: nil,179 RegisterNumber: nilRegisterNumber,180 IsJump: jumpX86,181 }182}183func archArm() *Arch {184 register := make(map[string]int16)185 // Create maps for easy lookup of instruction names etc.186 // Note that there is no list of names as there is for x86.187 for i := arm.REG_R0; i < arm.REG_SPSR; i++ {188 register[obj.Rconv(i)] = int16(i)189 }190 // Avoid unintentionally clobbering g using R10.191 delete(register, "R10")192 register["g"] = arm.REG_R10193 for i := 0; i < 16; i++ {194 register[fmt.Sprintf("C%d", i)] = int16(i)195 }196 // Pseudo-registers.197 register["SB"] = RSB198 register["FP"] = RFP199 register["PC"] = RPC200 register["SP"] = RSP201 registerPrefix := map[string]bool{202 "F": true,203 "R": true,204 }205 // special operands for DMB/DSB instructions206 register["MB_SY"] = arm.REG_MB_SY207 register["MB_ST"] = arm.REG_MB_ST208 register["MB_ISH"] = arm.REG_MB_ISH209 register["MB_ISHST"] = arm.REG_MB_ISHST210 register["MB_NSH"] = arm.REG_MB_NSH211 register["MB_NSHST"] = arm.REG_MB_NSHST212 register["MB_OSH"] = arm.REG_MB_OSH213 register["MB_OSHST"] = arm.REG_MB_OSHST214 instructions := make(map[string]obj.As)215 for i, s := range obj.Anames {216 instructions[s] = obj.As(i)217 }218 for i, s := range arm.Anames {219 if obj.As(i) >= obj.A_ARCHSPECIFIC {220 instructions[s] = obj.As(i) + obj.ABaseARM221 }222 }223 // Annoying aliases.224 instructions["B"] = obj.AJMP225 instructions["BL"] = obj.ACALL226 // MCR differs from MRC by the way fields of the word are encoded.227 // (Details in arm.go). Here we add the instruction so parse will find228 // it, but give it an opcode number known only to us.229 instructions["MCR"] = aMCR230 return &Arch{231 LinkArch: &arm.Linkarm,232 Instructions: instructions,233 Register: register,234 RegisterPrefix: registerPrefix,235 RegisterNumber: armRegisterNumber,236 IsJump: jumpArm,237 }238}239func archArm64() *Arch {240 register := make(map[string]int16)241 // Create maps for easy lookup of instruction names etc.242 // Note that there is no list of names as there is for 386 and amd64.243 register[obj.Rconv(arm64.REGSP)] = int16(arm64.REGSP)244 for i := arm64.REG_R0; i <= arm64.REG_R31; i++ {245 register[obj.Rconv(i)] = int16(i)246 }247 // Rename R18 to R18_PLATFORM to avoid accidental use.248 register["R18_PLATFORM"] = register["R18"]249 delete(register, "R18")250 for i := arm64.REG_F0; i <= arm64.REG_F31; i++ {251 register[obj.Rconv(i)] = int16(i)252 }253 for i := arm64.REG_V0; i <= arm64.REG_V31; i++ {254 register[obj.Rconv(i)] = int16(i)255 }256 // System registers.257 for i := 0; i < len(arm64.SystemReg); i++ {258 register[arm64.SystemReg[i].Name] = arm64.SystemReg[i].Reg259 }260 register["LR"] = arm64.REGLINK261 register["DAIFSet"] = arm64.REG_DAIFSet262 register["DAIFClr"] = arm64.REG_DAIFClr263 register["PLDL1KEEP"] = arm64.REG_PLDL1KEEP264 register["PLDL1STRM"] = arm64.REG_PLDL1STRM265 register["PLDL2KEEP"] = arm64.REG_PLDL2KEEP266 register["PLDL2STRM"] = arm64.REG_PLDL2STRM267 register["PLDL3KEEP"] = arm64.REG_PLDL3KEEP268 register["PLDL3STRM"] = arm64.REG_PLDL3STRM269 register["PLIL1KEEP"] = arm64.REG_PLIL1KEEP270 register["PLIL1STRM"] = arm64.REG_PLIL1STRM271 register["PLIL2KEEP"] = arm64.REG_PLIL2KEEP272 register["PLIL2STRM"] = arm64.REG_PLIL2STRM273 register["PLIL3KEEP"] = arm64.REG_PLIL3KEEP274 register["PLIL3STRM"] = arm64.REG_PLIL3STRM275 register["PSTL1KEEP"] = arm64.REG_PSTL1KEEP276 register["PSTL1STRM"] = arm64.REG_PSTL1STRM277 register["PSTL2KEEP"] = arm64.REG_PSTL2KEEP278 register["PSTL2STRM"] = arm64.REG_PSTL2STRM279 register["PSTL3KEEP"] = arm64.REG_PSTL3KEEP280 register["PSTL3STRM"] = arm64.REG_PSTL3STRM281 // Conditional operators, like EQ, NE, etc.282 register["EQ"] = arm64.COND_EQ283 register["NE"] = arm64.COND_NE284 register["HS"] = arm64.COND_HS285 register["CS"] = arm64.COND_HS286 register["LO"] = arm64.COND_LO287 register["CC"] = arm64.COND_LO288 register["MI"] = arm64.COND_MI289 register["PL"] = arm64.COND_PL290 register["VS"] = arm64.COND_VS291 register["VC"] = arm64.COND_VC292 register["HI"] = arm64.COND_HI293 register["LS"] = arm64.COND_LS294 register["GE"] = arm64.COND_GE295 register["LT"] = arm64.COND_LT296 register["GT"] = arm64.COND_GT297 register["LE"] = arm64.COND_LE298 register["AL"] = arm64.COND_AL299 register["NV"] = arm64.COND_NV300 // Pseudo-registers.301 register["SB"] = RSB302 register["FP"] = RFP303 register["PC"] = RPC304 register["SP"] = RSP305 // Avoid unintentionally clobbering g using R28.306 delete(register, "R28")307 register["g"] = arm64.REG_R28308 registerPrefix := map[string]bool{309 "F": true,310 "R": true,311 "V": true,312 }313 instructions := make(map[string]obj.As)314 for i, s := range obj.Anames {315 instructions[s] = obj.As(i)316 }317 for i, s := range arm64.Anames {318 if obj.As(i) >= obj.A_ARCHSPECIFIC {319 instructions[s] = obj.As(i) + obj.ABaseARM64320 }321 }322 // Annoying aliases.323 instructions["B"] = arm64.AB324 instructions["BL"] = arm64.ABL325 return &Arch{326 LinkArch: &arm64.Linkarm64,327 Instructions: instructions,328 Register: register,329 RegisterPrefix: registerPrefix,330 RegisterNumber: arm64RegisterNumber,331 IsJump: jumpArm64,332 }333}334func archPPC64(linkArch *obj.LinkArch) *Arch {335 register := make(map[string]int16)336 // Create maps for easy lookup of instruction names etc.337 // Note that there is no list of names as there is for x86.338 for i := ppc64.REG_R0; i <= ppc64.REG_R31; i++ {339 register[obj.Rconv(i)] = int16(i)340 }341 for i := ppc64.REG_F0; i <= ppc64.REG_F31; i++ {342 register[obj.Rconv(i)] = int16(i)343 }344 for i := ppc64.REG_V0; i <= ppc64.REG_V31; i++ {345 register[obj.Rconv(i)] = int16(i)346 }347 for i := ppc64.REG_VS0; i <= ppc64.REG_VS63; i++ {348 register[obj.Rconv(i)] = int16(i)349 }350 for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ {351 register[obj.Rconv(i)] = int16(i)352 }353 for i := ppc64.REG_MSR; i <= ppc64.REG_CR; i++ {354 register[obj.Rconv(i)] = int16(i)355 }356 for i := ppc64.REG_CR0LT; i <= ppc64.REG_CR7SO; i++ {357 register[obj.Rconv(i)] = int16(i)358 }359 register["CR"] = ppc64.REG_CR360 register["XER"] = ppc64.REG_XER361 register["LR"] = ppc64.REG_LR362 register["CTR"] = ppc64.REG_CTR363 register["FPSCR"] = ppc64.REG_FPSCR364 register["MSR"] = ppc64.REG_MSR365 // Pseudo-registers.366 register["SB"] = RSB367 register["FP"] = RFP368 register["PC"] = RPC369 // Avoid unintentionally clobbering g using R30.370 delete(register, "R30")371 register["g"] = ppc64.REG_R30372 registerPrefix := map[string]bool{373 "CR": true,374 "F": true,375 "R": true,376 "SPR": true,377 }378 instructions := make(map[string]obj.As)379 for i, s := range obj.Anames {380 instructions[s] = obj.As(i)381 }382 for i, s := range ppc64.Anames {383 if obj.As(i) >= obj.A_ARCHSPECIFIC {384 instructions[s] = obj.As(i) + obj.ABasePPC64385 }386 }387 // Annoying aliases.388 instructions["BR"] = ppc64.ABR389 instructions["BL"] = ppc64.ABL390 return &Arch{391 LinkArch: linkArch,392 Instructions: instructions,393 Register: register,394 RegisterPrefix: registerPrefix,395 RegisterNumber: ppc64RegisterNumber,396 IsJump: jumpPPC64,397 }398}399func archMips(linkArch *obj.LinkArch) *Arch {400 register := make(map[string]int16)401 // Create maps for easy lookup of instruction names etc.402 // Note that there is no list of names as there is for x86.403 for i := mips.REG_R0; i <= mips.REG_R31; i++ {404 register[obj.Rconv(i)] = int16(i)405 }406 for i := mips.REG_F0; i <= mips.REG_F31; i++ {407 register[obj.Rconv(i)] = int16(i)408 }409 for i := mips.REG_M0; i <= mips.REG_M31; i++ {410 register[obj.Rconv(i)] = int16(i)411 }412 for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ {413 register[obj.Rconv(i)] = int16(i)414 }415 register["HI"] = mips.REG_HI416 register["LO"] = mips.REG_LO417 // Pseudo-registers.418 register["SB"] = RSB419 register["FP"] = RFP420 register["PC"] = RPC421 // Avoid unintentionally clobbering g using R30.422 delete(register, "R30")423 register["g"] = mips.REG_R30424 registerPrefix := map[string]bool{425 "F": true,426 "FCR": true,427 "M": true,428 "R": true,429 }430 instructions := make(map[string]obj.As)431 for i, s := range obj.Anames {432 instructions[s] = obj.As(i)433 }434 for i, s := range mips.Anames {435 if obj.As(i) >= obj.A_ARCHSPECIFIC {436 instructions[s] = obj.As(i) + obj.ABaseMIPS437 }438 }439 // Annoying alias.440 instructions["JAL"] = mips.AJAL441 return &Arch{442 LinkArch: linkArch,443 Instructions: instructions,444 Register: register,445 RegisterPrefix: registerPrefix,446 RegisterNumber: mipsRegisterNumber,447 IsJump: jumpMIPS,448 }449}450func archMips64(linkArch *obj.LinkArch) *Arch {451 register := make(map[string]int16)452 // Create maps for easy lookup of instruction names etc.453 // Note that there is no list of names as there is for x86.454 for i := mips.REG_R0; i <= mips.REG_R31; i++ {455 register[obj.Rconv(i)] = int16(i)456 }457 for i := mips.REG_F0; i <= mips.REG_F31; i++ {458 register[obj.Rconv(i)] = int16(i)459 }460 for i := mips.REG_M0; i <= mips.REG_M31; i++ {461 register[obj.Rconv(i)] = int16(i)462 }463 for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ {464 register[obj.Rconv(i)] = int16(i)465 }466 for i := mips.REG_W0; i <= mips.REG_W31; i++ {467 register[obj.Rconv(i)] = int16(i)468 }469 register["HI"] = mips.REG_HI470 register["LO"] = mips.REG_LO471 // Pseudo-registers.472 register["SB"] = RSB473 register["FP"] = RFP474 register["PC"] = RPC475 // Avoid unintentionally clobbering g using R30.476 delete(register, "R30")477 register["g"] = mips.REG_R30478 // Avoid unintentionally clobbering RSB using R28.479 delete(register, "R28")480 register["RSB"] = mips.REG_R28481 registerPrefix := map[string]bool{482 "F": true,483 "FCR": true,484 "M": true,485 "R": true,486 "W": true,487 }488 instructions := make(map[string]obj.As)489 for i, s := range obj.Anames {490 instructions[s] = obj.As(i)491 }492 for i, s := range mips.Anames {493 if obj.As(i) >= obj.A_ARCHSPECIFIC {494 instructions[s] = obj.As(i) + obj.ABaseMIPS495 }496 }497 // Annoying alias.498 instructions["JAL"] = mips.AJAL499 return &Arch{500 LinkArch: linkArch,501 Instructions: instructions,502 Register: register,503 RegisterPrefix: registerPrefix,504 RegisterNumber: mipsRegisterNumber,505 IsJump: jumpMIPS,506 }507}508func archRISCV64(shared bool) *Arch {509 register := make(map[string]int16)510 // Standard register names.511 for i := riscv.REG_X0; i <= riscv.REG_X31; i++ {512 // Disallow X3 in shared mode, as this will likely be used as the513 // GP register, which could result in problems in non-Go code,514 // including signal handlers.515 if shared && i == riscv.REG_GP {516 continue517 }518 if i == riscv.REG_TP || i == riscv.REG_G {519 continue520 }521 name := fmt.Sprintf("X%d", i-riscv.REG_X0)522 register[name] = int16(i)523 }524 for i := riscv.REG_F0; i <= riscv.REG_F31; i++ {525 name := fmt.Sprintf("F%d", i-riscv.REG_F0)526 register[name] = int16(i)527 }528 // General registers with ABI names.529 register["ZERO"] = riscv.REG_ZERO530 register["RA"] = riscv.REG_RA531 register["SP"] = riscv.REG_SP532 register["GP"] = riscv.REG_GP533 register["TP"] = riscv.REG_TP534 register["T0"] = riscv.REG_T0535 register["T1"] = riscv.REG_T1536 register["T2"] = riscv.REG_T2537 register["S0"] = riscv.REG_S0538 register["S1"] = riscv.REG_S1539 register["A0"] = riscv.REG_A0540 register["A1"] = riscv.REG_A1541 register["A2"] = riscv.REG_A2542 register["A3"] = riscv.REG_A3543 register["A4"] = riscv.REG_A4544 register["A5"] = riscv.REG_A5545 register["A6"] = riscv.REG_A6546 register["A7"] = riscv.REG_A7547 register["S2"] = riscv.REG_S2548 register["S3"] = riscv.REG_S3549 register["S4"] = riscv.REG_S4550 register["S5"] = riscv.REG_S5551 register["S6"] = riscv.REG_S6552 register["S7"] = riscv.REG_S7553 register["S8"] = riscv.REG_S8554 register["S9"] = riscv.REG_S9555 register["S10"] = riscv.REG_S10556 // Skip S11 as it is the g register.557 register["T3"] = riscv.REG_T3558 register["T4"] = riscv.REG_T4559 register["T5"] = riscv.REG_T5560 register["T6"] = riscv.REG_T6561 // Go runtime register names.562 register["g"] = riscv.REG_G563 register["CTXT"] = riscv.REG_CTXT564 register["TMP"] = riscv.REG_TMP565 // ABI names for floating point register.566 register["FT0"] = riscv.REG_FT0567 register["FT1"] = riscv.REG_FT1568 register["FT2"] = riscv.REG_FT2569 register["FT3"] = riscv.REG_FT3570 register["FT4"] = riscv.REG_FT4571 register["FT5"] = riscv.REG_FT5572 register["FT6"] = riscv.REG_FT6573 register["FT7"] = riscv.REG_FT7574 register["FS0"] = riscv.REG_FS0575 register["FS1"] = riscv.REG_FS1576 register["FA0"] = riscv.REG_FA0577 register["FA1"] = riscv.REG_FA1578 register["FA2"] = riscv.REG_FA2579 register["FA3"] = riscv.REG_FA3580 register["FA4"] = riscv.REG_FA4581 register["FA5"] = riscv.REG_FA5582 register["FA6"] = riscv.REG_FA6583 register["FA7"] = riscv.REG_FA7584 register["FS2"] = riscv.REG_FS2585 register["FS3"] = riscv.REG_FS3586 register["FS4"] = riscv.REG_FS4587 register["FS5"] = riscv.REG_FS5588 register["FS6"] = riscv.REG_FS6589 register["FS7"] = riscv.REG_FS7590 register["FS8"] = riscv.REG_FS8591 register["FS9"] = riscv.REG_FS9592 register["FS10"] = riscv.REG_FS10593 register["FS11"] = riscv.REG_FS11594 register["FT8"] = riscv.REG_FT8595 register["FT9"] = riscv.REG_FT9596 register["FT10"] = riscv.REG_FT10597 register["FT11"] = riscv.REG_FT11598 // Pseudo-registers.599 register["SB"] = RSB600 register["FP"] = RFP601 register["PC"] = RPC602 instructions := make(map[string]obj.As)603 for i, s := range obj.Anames {604 instructions[s] = obj.As(i)605 }606 for i, s := range riscv.Anames {607 if obj.As(i) >= obj.A_ARCHSPECIFIC {608 instructions[s] = obj.As(i) + obj.ABaseRISCV609 }610 }611 return &Arch{612 LinkArch: &riscv.LinkRISCV64,613 Instructions: instructions,614 Register: register,615 RegisterPrefix: nil,616 RegisterNumber: nilRegisterNumber,617 IsJump: jumpRISCV,618 }619}620func archS390x() *Arch {621 register := make(map[string]int16)622 // Create maps for easy lookup of instruction names etc.623 // Note that there is no list of names as there is for x86.624 for i := s390x.REG_R0; i <= s390x.REG_R15; i++ {625 register[obj.Rconv(i)] = int16(i)626 }627 for i := s390x.REG_F0; i <= s390x.REG_F15; i++ {628 register[obj.Rconv(i)] = int16(i)629 }630 for i := s390x.REG_V0; i <= s390x.REG_V31; i++ {631 register[obj.Rconv(i)] = int16(i)632 }633 for i := s390x.REG_AR0; i <= s390x.REG_AR15; i++ {634 register[obj.Rconv(i)] = int16(i)635 }636 register["LR"] = s390x.REG_LR637 // Pseudo-registers.638 register["SB"] = RSB639 register["FP"] = RFP640 register["PC"] = RPC641 // Avoid unintentionally clobbering g using R13.642 delete(register, "R13")643 register["g"] = s390x.REG_R13644 registerPrefix := map[string]bool{645 "AR": true,646 "F": true,647 "R": true,648 }649 instructions := make(map[string]obj.As)650 for i, s := range obj.Anames {651 instructions[s] = obj.As(i)652 }653 for i, s := range s390x.Anames {654 if obj.As(i) >= obj.A_ARCHSPECIFIC {655 instructions[s] = obj.As(i) + obj.ABaseS390X656 }657 }658 // Annoying aliases.659 instructions["BR"] = s390x.ABR660 instructions["BL"] = s390x.ABL661 return &Arch{662 LinkArch: &s390x.Links390x,663 Instructions: instructions,664 Register: register,665 RegisterPrefix: registerPrefix,666 RegisterNumber: s390xRegisterNumber,667 IsJump: jumpS390x,668 }669}670func archWasm() *Arch {671 instructions := make(map[string]obj.As)672 for i, s := range obj.Anames {673 instructions[s] = obj.As(i)674 }675 for i, s := range wasm.Anames {676 if obj.As(i) >= obj.A_ARCHSPECIFIC {677 instructions[s] = obj.As(i) + obj.ABaseWasm678 }679 }680 return &Arch{681 LinkArch: &wasm.Linkwasm,682 Instructions: instructions,683 Register: wasm.Register,684 RegisterPrefix: nil,685 RegisterNumber: nilRegisterNumber,686 IsJump: jumpWasm,687 }688}...
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