Best Syzkaller code snippet using powerpc.Encode
powerpc_encoding.go
Source:powerpc_encoding.go
...73 }74 }75 return result76}77// EncodeInstrBForm handles encoding a given opcode, BO, BI, BD, AA and LK.78// I-form assumes:79// - 6 bits for the opcode80// - 5 bits for BO81// - 5 bits for BI82// - 24 bits for BD83// - 1 bit for absolute (AA)84// - 1 bit for should store in link register (LK)85func EncodeInstrBForm(opcode byte, BO Register, BI Register, BD [3]byte, AA bool, LK bool) Instruction {86 opBits := getBits(opcode)87 bOBits := getBits(byte(BO))88 bIBits := getBits(byte(BI))89 bDTwo := getBits(BD[1])90 bDThree := getBits(BD[2])91 instr := [4]Bits{92 {93 // We need the upper six bits for our opcode.94 opBits[2], opBits[3], opBits[4], opBits[5], opBits[6], opBits[7],95 // We need the upper five bits for BO and BI.96 bOBits[3], bOBits[4],97 },98 {99 bOBits[5], bOBits[6], bOBits[7], bIBits[3], bIBits[4], bIBits[5], bIBits[6], bIBits[7],100 },101 {102 // We need the upper 14 bits for the destination branch (BD).103 bDTwo[2], bDTwo[3], bDTwo[4], bDTwo[5], bDTwo[6], bDTwo[7], bDThree[0], bDThree[1],104 },105 {106 bDThree[2], bDThree[3], bDThree[4], bDThree[5], bDThree[6], bDThree[7],107 AA,108 LK,109 },110 }111 return Instruction{instr[0].getByte(), instr[1].getByte(), instr[2].getByte(), instr[3].getByte()}112}113// EncodeInstrDForm handles encoding a given opcode, RT, RA and SI.114// D-form assumes:115// - 6 bits for the opcode116// - 5 for rT117// - 5 for rA118// - 16 for SI119func EncodeInstrDForm(opcode byte, rT Register, rA Register, value uint16) Instruction {120 var instr [2]Bits121 opBits := getBits(opcode)122 rTBits := getBits(byte(rT))123 rABits := getBits(byte(rA))124 instr[0] = Bits{125 // We need the upper six bits for our opcode.126 opBits[2],127 opBits[3],128 opBits[4],129 opBits[5],130 opBits[6],131 opBits[7],132 // Next, the lower two bits for rT.133 rTBits[3],134 rTBits[4],135 }136 instr[1] = Bits{137 // Third, the lower three bits for rT.138 rTBits[5],139 rTBits[6],140 rTBits[7],141 // Finally, all five lowest bits for rA.142 rABits[3],143 rABits[4],144 rABits[5],145 rABits[6],146 rABits[7],147 }148 firstInstr := instr[0].getByte()149 secondInstr := instr[1].getByte()150 valByte := twoByte(value)151 return Instruction{firstInstr, secondInstr, valByte[0], valByte[1]}152}153// EncodeInstrIForm handles encoding a given opcode, LI, AA and LK.154// I-form assumes:155// - 6 bits for the opcode156// - 24 bits for LI157// - 1 bit for absolute (AA)158// - 1 bit for should store in link register (LK)159func EncodeInstrIForm(opcode byte, LI [3]byte, AA bool, LK bool) Instruction {160 opBits := getBits(opcode)161 liOne := getBits(LI[0])162 liTwo := getBits(LI[1])163 liThree := getBits(LI[2])164 instr := [4]Bits{165 {166 // We need the upper six bits for our opcode.167 opBits[2], opBits[3], opBits[4], opBits[5], opBits[6], opBits[7],168 // Otherwise, copy LI as-is.169 liOne[0], liOne[1],170 },171 {172 liOne[2], liOne[3], liOne[4], liOne[5], liOne[6], liOne[7], liTwo[0], liTwo[1],173 },174 {175 liTwo[2], liTwo[3], liTwo[4], liTwo[5], liTwo[6], liTwo[7], liThree[0], liThree[1],176 },177 {178 liThree[2], liThree[3], liThree[4], liThree[5], liThree[6], liThree[7],179 // Copy AA and LK as-is.180 AA,181 LK,182 },183 }184 return Instruction{instr[0].getByte(), instr[1].getByte(), instr[2].getByte(), instr[3].getByte()}185}186// EncodeInstrXForm handles encoding a given opcode, rS, rA, rB, an extended opcode and rC.187// X-form assumes:188// - 6 bits for the opcode189// - 5 bits for rS190// - 5 bits for rA191// - 5 bits for rB192// - 10 bits for XO (extended opcode)193// - 1 bit for rC (dependent on the condition register)194func EncodeInstrXForm(opcode byte, rS Register, rA Register, rB Register, XO uint16, rC bool) Instruction {195 opBits := getBits(opcode)196 rSBits := getBits(byte(rS))197 rABits := getBits(byte(rA))198 rBBits := getBits(byte(rB))199 extendedOP1 := getBits(twoByte(XO)[0])200 extendedOP2 := getBits(twoByte(XO)[1])201 instr := [4]Bits{202 {203 // We need the upper six bits for our opcode.204 opBits[2], opBits[3], opBits[4], opBits[5], opBits[6], opBits[7],205 // We need the upper five bits for rS, rA and rB.206 rSBits[3], rSBits[4],207 },208 {209 rSBits[5], rSBits[6], rSBits[7], rABits[3], rABits[4], rABits[5], rABits[6], rABits[7],210 },211 {212 // We need the upper 10 bits for the extended opcode.213 rBBits[3], rBBits[4], rBBits[5], rBBits[6], rBBits[7], extendedOP1[6], extendedOP1[7], extendedOP2[0],214 },215 {216 extendedOP2[1], extendedOP2[2], extendedOP2[3], extendedOP2[4], extendedOP2[5], extendedOP2[6], extendedOP2[7], rC,217 },218 }219 return Instruction{instr[0].getByte(), instr[1].getByte(), instr[2].getByte(), instr[3].getByte()}220}221// EncodeInstrXFXForm handles encoding a given opcode, rS, spr, an extended opcode and rC.222// XFX-form assumes:223// - 6 bits for the opcode224// - 5 bits for rS225// - 10 bits for spr (special-purpose register)226// - 10 bits for XO (extended opcode)227// - 1 bit for rC (dependent on the condition register)228func EncodeInstrXFXForm(opcode byte, rS Register, spr SpecialRegister, XO uint16, rC bool) Instruction {229 opBits := getBits(opcode)230 rSBits := getBits(byte(rS))231 sprBytes := twoByte(uint16(spr))232 sprBitsOne := getBits(sprBytes[0])233 sprBitsTwo := getBits(sprBytes[1])234 extendedOP1 := getBits(twoByte(XO)[0])235 extendedOP2 := getBits(twoByte(XO)[1])236 instr := [4]Bits{237 {238 // We need the upper six bits for our opcode.239 opBits[2], opBits[3], opBits[4], opBits[5], opBits[6], opBits[7],240 // We need the upper five bits for rS.241 rSBits[3], rSBits[4],242 },...
powerpc.go
Source:powerpc.go
...44 return [4]byte{0x4c, 0xc6, 0x31, 0x82}45}46// ADDI represents the addi PowerPC instruction.47func ADDI(rT Register, rA Register, value uint16) Instruction {48 return EncodeInstrDForm(14, rT, rA, value)49}50// LI represents the li mnemonic on PowerPC.51func LI(rT Register, value uint16) Instruction {52 return ADDI(rT, 0, value)53}54// SUBI represents the subi mnemonic on PowerPC.55// TODO: handle negative values properly?56func SUBI(rT Register, rA Register, value uint16) Instruction {57 return ADDI(rT, 0, -value)58}59// ADDIS represents the addis PowerPC instruction.60func ADDIS(rT Register, rA Register, value uint16) Instruction {61 return EncodeInstrDForm(15, rT, rA, value)62}63// LIS represents the lis mnemonic on PowerPC.64func LIS(rT Register, value uint16) Instruction {65 return ADDIS(rT, 0, value)66}67// OR represents the or PowerPC instruction.68func OR(rS Register, rA Register, rB Register, rC bool) Instruction {69 return EncodeInstrXForm(31, rS, rA, rB, 444, rC)70}71// ORI represents the ori PowerPC instruction.72func ORI(rS Register, rA Register, value uint16) Instruction {73 return EncodeInstrDForm(24, rS, rA, value)74}75// STH represents the sth PowerPC instruction.76func STH(rS Register, offset uint16, rA Register) Instruction {77 return EncodeInstrDForm(44, rS, rA, offset)78}79// EIEIO represents the eieio PowerPC instruction.80func EIEIO() Instruction {81 return EncodeInstrXForm(31, 0, 0, 0, 854, false)82}83// STW represents the stw PowerPC instruction.84func STW(rS Register, offset uint16, rA Register) Instruction {85 return EncodeInstrDForm(36, rS, rA, offset)86}87// STB represents the stb PowerPC instruction.88func STB(rS Register, offset uint16, rA Register) Instruction {89 return EncodeInstrDForm(38, rS, rA, offset)90}91// LWZ represents the lwz PowerPC instruction.92func LWZ(rT Register, offset uint16, rA Register) Instruction {93 return EncodeInstrDForm(32, rT, rA, offset)94}95// NOP represents the nop mnemonic for PowerPC.96func NOP() Instruction {97 return ORI(R0, R0, 0)98}99// CMPWI represents the cmpwi mnemonic for PowerPC.100// It does not support any other CR fields asides from 0.101func CMPWI(rA Register, value uint16) Instruction {102 return EncodeInstrDForm(11, 0, rA, value)103}104// SYNC represents the sync PowerPC instruction.105func SYNC() Instruction {106 return EncodeInstrXForm(31, 0, 0, 0, 598, false)107}108// MTSPR represents the mtspr PowerPC instruction.109func MTSPR(spr SpecialRegister, rS Register) Instruction {110 return EncodeInstrXFXForm(31, rS, spr, 467, false)111}112// MFSPR represents the mfspr PowerPC instruction.113func MFSPR(rS Register, spr SpecialRegister) Instruction {114 return EncodeInstrXFXForm(31, rS, spr, 339, false)115}116// STWU represents the stwu PowerPC instruction.117func STWU(rS Register, rA Register, offset uint16) Instruction {118 return EncodeInstrDForm(37, rS, rA, offset)119}120// calcDestination determines the proper offset from a given121// calling address and target address.122func calcDestination(from uint, target uint) [3]byte {123 offset := target - from124 if offset > 0x00FFFFFF {125 offset = 0x10001 - (uint(int(from) - int(target)))126 }127 // Sign-extend by two bytes128 calc := uint32(offset >> 2)129 return uint24(calc)130}131// BL represents the bl PowerPC instruction.132// It calculates the offset from the given current address and the given133// target address, saving the current address in the link register. It then branches.134func BL(current uint, target uint) Instruction {135 return EncodeInstrIForm(18, calcDestination(current, target), false, true)136}137// B represents the b PowerPC instruction.138// It calculates the offset from the given current address139// and the given target address, and then branches.140func B(current uint, target uint) Instruction {141 return EncodeInstrIForm(18, calcDestination(current, target), false, false)142}143// BNE represents the bne PowerPC instruction.144// It calculates the offset from the given current address145// and the given target address, and then branches.146func BNE(current uint, target uint) Instruction {147 return EncodeInstrBForm(16, 4, 2, calcDestination(current, target), false, false)148}...
pseudo.go
Source:pseudo.go
...61 // ori rn,rn,name##@higher62 // rldicr rn,rn,32,3163 // oris rn,rn,name##@h64 // ori rn,rn,name##@l65 gen.byte(gen.imap["addis"].EncodeParam(map[string]uint{66 "RT": reg,67 "RA": 0, // In "addis", '0' means 0, not GPR0 .68 "SI": uint((v >> 48) & 0xffff)},69 nil))70 gen.byte(gen.imap["ori"].EncodeParam(map[string]uint{71 "RA": reg,72 "RS": reg,73 "UI": uint((v >> 32) & 0xffff)},74 nil))75 gen.byte(gen.imap["rldicr"].EncodeParam(map[string]uint{76 "RA": reg,77 "RS": reg,78 "SH": 32,79 "ME": 31},80 nil))81 gen.byte(gen.imap["oris"].EncodeParam(map[string]uint{82 "RA": reg,83 "RS": reg,84 "UI": uint((v >> 16) & 0xffff)},85 nil))86 gen.byte(gen.imap["ori"].EncodeParam(map[string]uint{87 "RA": reg,88 "RS": reg,89 "UI": uint(v & 0xffff)},90 nil))91}92func (gen *generator) sc(lev uint) {93 n := gen.r.Intn(9)94 // Valid hcall humbers at the momemt are: 4..0x45095 gen.ld64(3, uint64(gen.r.Intn(4+(0x450-4)/4)))96 for i := 4; i < n+4; i++ {97 gen.ld64(uint(i), gen.r.Uint64())98 }99 gen.byte(gen.imap["sc"].EncodeParam(map[string]uint{"LEV": lev}, nil))100}...
Encode
Using AI Code Generation
1import (2func main() {3 fmt.Println(stringutil.Reverse("!oG ,olleH"))4}5import (6func main() {7 fmt.Println(my_package.Reverse("!oG ,olleH"))8}9import (10func main() {11 fmt.Println(my_package.Reverse("!oG ,olleH"))12}
Encode
Using AI Code Generation
1import (2type powerpc struct {3}4func (p powerpc) String() string {5 return fmt.Sprintf("PowerPC %s %d", p.model, p.year)6}7func (p powerpc) Encode() string {8 return fmt.Sprintf("%s-%s-%d", p.arch, p.model, p.year)9}10func main() {11 p := powerpc{"PowerPC", "G5", 2003}12 s := p.Encode()13 for _, r := range s {14 z01.PrintRune(r)15 }16 z01.PrintRune('\n')17}18import (19type powerpc struct {20}21func (p powerpc) String() string {22 return fmt.Sprintf("PowerPC %s %d", p.model, p.year)23}24func (p powerpc) Encode() string {25 return fmt.Sprintf("%s-%s-%d", p.arch, p.model, p.year)26}27func main() {28 p := powerpc{"PowerPC", "G5", 2003}29 s := p.Encode()30 for _, r := range s {31 z01.PrintRune(r)32 }33 z01.PrintRune('\n')34}35import (36type powerpc struct {37}38func (p powerpc) String() string {39 return fmt.Sprintf("PowerPC %s %d", p.model, p.year)40}41func (p powerpc) Encode() string {42 return fmt.Sprintf("%s-%s-%d", p.arch, p.model, p.year)43}44func main() {45 p := powerpc{"PowerPC", "G5", 2003}46 s := p.Encode()47 for _, r := range s {48 z01.PrintRune(r)49 }50 z01.PrintRune('\n')51}
Encode
Using AI Code Generation
1import (2func main() {3 p := powerpc.NewPowerPC()4 fmt.Println(p.Encode("Hello World"))5}6import (7func main() {8 p := powerpc.NewPowerPC()9 fmt.Println(p.Decode("Hello World"))10}11import (12type PowerPC struct {13}14func NewPowerPC() *PowerPC {15 return &PowerPC{}16}17func (p *PowerPC) Encode(msg string) string {18 return fmt.Sprintf("Encoded: %s", msg)19}20func (p *PowerPC) Decode(msg string) string {21 return fmt.Sprintf("Decoded: %s", msg)22}
Encode
Using AI Code Generation
1import (2func main() {3 obj := powerpc.Powerpc{}4 obj.Encode()5}6import (7func main() {8 obj := powerpc.Powerpc{}9 obj.Decode()10}11import (12func main() {13 obj := intel.Intel{}14 obj.Encode()15}16import (17func main() {18 obj := intel.Intel{}19 obj.Decode()20}
Encode
Using AI Code Generation
1func main() {2 powerpc := new(Powerpc)3 powerpc.Encode("Hi")4}5type Powerpc struct {6}7func (p *Powerpc) Encode(message string) {8 fmt.Println("Powerpc: " + message)9}10func main() {11 dog := new(Dog)12 dog.Speak()13 cat := new(Cat)14 cat.Speak()15}16type Dog struct {17}18func (d *Dog) Speak() {19 fmt.Println("Dog says woof")20}21type Cat struct {22}23func (c *Cat) Speak() {24 fmt.Println("Cat says meow")25}
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